Embodiments of the present invention relate to calculation and placement of an adjustable dummy fill layer to improve semiconductor integrated circuit processing.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield require a finely tuned manufacturing process. Second order effects that might have been ignored a decade ago are now critical to cost-effective processing as will be explained in detail.
FIG. 1A is a schematic diagram of a 1T-1C ferroelectric random access memory (FeRAM) cell of the prior art. The memory cell includes an access transistor 108 coupled between a bit line 110 and a ferroelectric capacitor 104. The ferroelectric capacitor 104 is coupled between storage node 102 and a plate voltage (Vp) terminal 150. FIG. 1B is a cross sectional view of the ferroelectric memory cell of FIG. 1A as disclosed by copending application Ser. No. 11/756,372, filed May 31, 2007, and incorporated by reference herein in its entirety. Common identification numerals are used in multiple figures to indicate the same features. The memory cell includes N-channel access transistor 108 formed on P-substrate 120 having sidewall spacers 126 adjacent the gate region. Source/drain region 110 is connected to a bit line terminal. Source drain region 102 is connected to the storage node. Isolation region 122 separates the memory cell from adjacent memory cells in the memory array. A first dielectric region 130 overlies the access transistor 108. A contact region (CONT) 128 is formed in the dielectric region 130 to electrically connect one plate 140 of ferroelectric capacitor 104 to the storage node 102.
The ferroelectric capacitor 104 is a composite stack formed in layers and etched with a single mask step. The lower plate 140 is preferably formed of titanium aluminum nitride (TiAlN) in conductive contact with iridium layer 142. Likewise, the upper plate 148 is preferably formed of titanium aluminum nitride (TiAlN) in conductive contact with iridium layer 146. The upper and lower plates are separated by ferroelectric layer 144. The ferroelectric layer 144 is preferably formed of lead zirconate titanate (PZT) or strontium bismuth tantalite (SBT). A second dielectric region 160 overlies the ferroelectric capacitor 104. Plate voltage lead (MET1) 150 is formed on this second dielectric region and connected to the top plate 148 of the ferroelectric capacitor 104 by a first via region (VIAO). In areas of the semiconductor memory where there are no memory cells, VIAO may directly contact CONT to electrically connect MET1 to underlying gate or source/drain regions.
A significant problem disclosed in the prior art involves re-deposition of noble metal components (e.g. Pt, Pd, Ag, Au, Ir) on the sidewalls of the ferroelectric capacitor 104 during plasma etch. Such re-deposition may cause the ferroelectric capacitor to leak or even completely short the upper and lower plates, thereby reducing the overall yield of the semiconductor memory device. The prior art discloses a significant yield improvement is possible by controlling the sidewall slope of the ferroelectric capacitor to a range of 78° to 88° with respect to the surface of dielectric layer 130. This sidewall slope advantageously reduces the re-deposition of noble metal components without a significant reduction of area of the ferroelectric capacitor 104. The present inventors have discovered other factors that influence re-deposition of noble metal components on sidewalls of the ferroelectric capacitor 104 as will be discussed in detail. There is therefore a need to further improve the method of forming ferroelectric capacitors.